MEDIA ADVISORY
For more information, contact:
CO-DESIGN, GET2CHIP HOST SEMINAR TO DEMONSTRATE PRACTICAL BEHAVIOR TO GATE DESIGN FLOW PRODUCTIVITY
"Breaking the RTL Barrier"
WHAT: "Breaking the RTL Barrier," a forum for designers to learn more about.
WHEN: Tuesday, January 30, from 10 a.m. - noon; 2 p.m - 4 p.m.
WHERE: Westin Hotel in Santa Clara, Calif. (next to the Santa Clara Convention Center, location of DesignCon)
WHY: The SUPERLOG language from Co-Design Automation allows Verilog models to be evolved using abstract modeling constructs and verification capabilities. With SUPERLOG driving Get2Chip's VOLARE SL architectural synthesizer, abstract behavioral models may easily be transformed into efficient netlists. Co-Design's SYSTEMSIM simulator allows fast verification of the SUPERLOG model, together with powerful, integrated testbench capabilities and seamless C/C++ incorporation.
WHO: Hosted by Co-Design Automation Inc. and Get2Chip.com Inc.
Keynote address by:
RSVP: David Kelf, vice president of marketing at Co-Design Automation
Telephone: (617) 571-9883 or FAX: (781) 662-2281
Email: davek@co-design.com
Lauro Rizzatti, vice president of marketing at Get2Chip.com
Telephone: (408) 436-6779
Lauror@get2chip.com
# # #
|
|
CaféTalk
